mitsubishi semiconductor PS11012 flat-base type insulated type jan. 2000 1 cbu+ 2 cbu 3 cbv+ 4 cbv 5 cbw+ 6 cbw 7 gnd 8 nc 9 vdh 10 cl 11 fo1 12 fo2 13 fo3 14 cu 15 cv 16 cw 17 up 18 vp 19 wp 20 un 21 vn 22 wn 23 br 31 r 32 s 33 t 34 p1 35 p2 36 n 37 b 38 u 39 v 40 w 2 0.3 54 0.5 0.5 0.03 0.8 0~0.8 0~0.8 0.4 0.5 62 1 20.4 1 27 1 84.2 1 72 0.8 17.6 0.5 5.08 0.3 5 9 = 45.72 0.8 4-r2 2-r4 0.5 2 2 4.14 4 0.5 4 24 0.6 8.5 12 (12.25) 50 6 2 24 44 12 34 56 789 10 1112 13 141516 171819 2021 23 31 32 33 34 35 36 37 38 39 40 22 terminals assignment: 2- f 4 1.2 label 3.5 ] ] ] ] control pin top portion details ] main terminal top portion details 0.3 0.5 0 12 0.6 0.35max 0.5 0 PS11012 integrated functions and features ? converter bridge for 3 phase ac-to-dc power conversion. ? circuit for dynamic braking of motor regenerative energy. ? 3-phase igbt inverter bridge configured by the latest 3rd. generation igbt and diode technology. ? inverter output current capability i o (note 1): application acoustic noise-less 0.2kw/ac200v class 3 phase inverter and other motor control applica- tions package outlines mitsubishi semiconductor PS11012 flat-base type insulated type (note 1) : the inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : i op = i o ? ` 2 (fig. 1) type name PS11012 100% load 1.5a (rms) 150% over load 2.25a (rms), 1min integrated drive, protection and system control functions: ? for inverter side upper-leg igbts : drive circuit, high voltage isolated high-speed level shifting, short circuit protection ( sc). bootstrap circuit supply scheme (single drive power supply) and under voltage protection (uv). ? for inverter side lower-leg igbts : drive circuit, short circuit protection (sc). control supply circuit under- & over- voltage protection (ov/uv). system over temperature protection (ot). fault output signaling circuit (f o ) and current limit warn- ing signal output (cl). ? for brake circuit igbt : drive circuit ? warning and fault signaling : f o1 : short circuit protection for lower-leg igbts and input interlocking against spurious arm shoot-through. f o2 : n-side control supply abnormality locking (ov/uv). f o3 : system over-temperature protection (ot). cl : warning for inverter current overload condition ? for system feedback control : analogue signal feedback reproducing actual inverter output phase currents (3 f ). ? input interface : 5v cmos/ttl compatible, schmitt trigger input, and arm-shoot-through interlock protection.
mitsubishi semiconductor PS11012 flat-base type insulated type jan. 2000 each output igbt collector current brake igbt collector current brake diode anode current internal functions block diagram (fig. 2) v v 450 500 applied between p2-n applied between p2-n, surge-value applied between p-u, v, w, br or u, v, w, br-n applied between p-u, v, w, br or u, v, w, br-n t c = 25 c note: ( ) means i c peak value supply voltage supply voltage (surge) v cc v cc(surge) condition symbol item ratings unit maximum ratings (tj = 25 c) inverter part (including brake part) v p or v n v p(s) or v n(s) i c ( i cp ) i c (i cp ) i f (i fp ) each output igbt collector-emitter static voltage each output igbt collector-emitter switching surge voltage 600 600 4 ( 8) 2 (4) 2 (4) v v a a a v 20 fault output supply voltage fault output current current-limit warning (cl) output voltage cl output current analogue current signal output current applied between v dh -gnd, c bu+ -c buC , c bv+ -c bvC , c bw+ -c bwC applied between u p v p w p u n v n w n b r -gnd applied between f o1 f o2 f o3 -gnd sink current of f o1 f o2 f o3 applied between cl-gnd sink current of cl sink current of cu cv cw v dh , v db supply voltage symbol item ratings unit control part condition v fo i fo v cl i cl i co v cin input signal voltage C0.5 ~ 7.5 C0.5 ~ 7 15 C0.5 ~ 7 15 1 v v ma v ma ma 3 f rectifying circuit 1 cycle at 60hz, peak value non-repetitive value for one cycle of surge current condition symbol item ratings unit v rrm ea i o i fsm i 2 t repetitive peak reverse voltage recommended ac input voltage dc output current surge (non-repetitive) forward current i 2 t for fusing 800 220 25 138 80 v v a a a 2 s converter part (15v line) vdh gnd cucvcw u p v p w p u n v n w n b r cl fo1 fo2 fo3 b p2 p1 r s t c z n m w v u ac200v line input c3 ; 3.3 m f or more, tight tolerance, temp-compensated electrolytic type (note : the value may change depending on the type pwm control scheme used in the applied system) c4 ; 2 m f r-category ceramic condenser for noise filtering. c2 ; 3.3 m f or more fo logic protection circuit level shifter drive circuit drive curcuit trig signal conditioning current sensing circuit protection circuit control supply fault sense z : surge absorber. c : ac filter (ceramic condenser 2.2~6.5nf) [note : additionally an appropriate line-to line surge absorber circuit maybe necessary depending on the application environment]. ac 200v line output brake resistor connection, inrush prevention circuit, etc. note 1) to prevent chances of signal oscillation, an rc coupling at each output is recommended. (see also fig.10) note 2) by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu, without any opto or transformer isolation ispossible. (see also fig.10) note 3) all these outputs are open collector type. each signal line should be pulled up to plus side of the 5v power supply wit h approximately 5.1k w resistance. (see also fig.10) note 4) the wiring between power dc link capacitor and p/n terminals should be as short as possible to protect the asipm agains t catastrophic high surge voltage. for extra precaution, a small film type snubber capacitor (0.1~0.22 m f, high voltage type) is recommended to be mounted close to these p and n dc powerinput pins. analogue signal output corresponding to each phase current (5v line) note 1) each phase input (pwm) (5v line) note 2) fault output (5v line) note 3) cbu cbu+ cbv cbv+ cbw cbw+ c4,c3 application specific intelligent power module t.s. c2
mitsubishi semiconductor PS11012 flat-base type insulated type jan. 2000 tc 6.1 6.1 7.3 6.1 4.8 0.053 c/w c/w c/w c/w c/w c/w junction to case thermal resistance condition symbol item ratings unit (note 2) (fig. 3) 60 hz sinusoidal ac applied between all terminals and the base plate for 1 minute. mounting screw: m3.5 t j t stg t c v iso junction temperature storage temperature module case operating temperature isolation voltage mounting torque C20 ~ +125 C40 ~ +125 C20 ~ +100 2500 0.78 ~ 1.27 c c c vrms kgcm total system note 2) the item defines the maximum junction temperature for the power elements (igbt/diode) of the asipm to ensure safe opera tion. how- ever, these power elements can endure junction temperature as high as 150 c instantaneously . to make use of this additional tem- perature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use. condition symbol item ratings inverter igbt (1/6) inverter fwdi (1/6) brake igbt brake fwdi converter di (1/6) case to fin, thermal grease applied (1 module) rth(j-c) q rth(j-c) f rth(j-c) qb rth(j-c) fb rth(j-c) fr rth(c-f) min. thermal resistance typ. max. unit (fig. 3) case temperature measurement point (3mm from the base surface) contact thermal resistance 0.1 v cc 400v, input = on (one-shot) tj = 125 c start 13.5v v dh = v db 16.5v v cc 400v, tj 125 c, ic < i ol (cl) operation level, input = on 13.5v v dh = v db 16.5v v v v fbr i rrm v fr ton tc(on) toff tc(off) trr collector-emitter saturation voltage fwdi forward voltage brake igbt collector-emitter saturation voltage brake diode forward voltage converter diode reverse current converter diode voltage switching times fwd reverse recovery time v ce(sat) v ec ratings v dh = v db = 15v, input = on, tj = 25 c, i c = 4a condition symbol item min. typ. max. unit ? no destruction ? f o output by protection operation electrical characteristics (tj = 25 c, v dh = 15v, v db = 15v unless otherwise noted) tj = 25 c, i c = C4a, input = off ? no destruction ? no protecting operation ? no f o output v ce(sat)br v dh = 15v, input = on, tj = 25 c, i c = 2a tj = 25 c, i f = 2a, input = off v r = v rrm , tj = 125 c tj = 25 c, i f = 5a 1/2 bridge inductive load, input = on v cc = 300v, ic = 4a, tj = 125 c v dh = 15v, v db = 15v note : ton, toff include delay time of the internal control circuit short circuit endurance (output, arm, and load, short circuit modes) switching soa 0.3 0.6 0.2 1.1 0.35 2.9 2.9 3.5 2.9 8 1.5 1.5 0.6 1.8 1.0 v v ma v m s m s m s m s m s
mitsubishi semiconductor PS11012 flat-base type insulated type jan. 2000 d v dh , d v db v cin(on) v cin(off) f pwm t dead supply voltage ripple input on voltage input off voltage pwm input frequency arm shoot-through blocking time ty p. recommended conditions v 400 (max.) applied across p2-n terminals condition symbol item ratings v cc supply voltage unit min. 150 trip level reset level trip level reset level trip level reset level trip level reset level filter time idle active t d(read) i ol i cl(h) i cl(l) sc ot otr uv dh uv dhr ov dh ov dhr uv db uv dbr t dv i fo(h) i fo(l) t int v co v c+ (200%) v cC (200%) | d v co | v c+ v cC d v c (200%) ic = 0a ic = i op (200%) ic = Ci op (200%) input on threshold voltage input off threshold voltage input pull-up resistor 1.87 0.77 2.97 4.0 6.95 100 11.05 11.55 18.00 16.50 10.0 10.5 t c = C20 c ~ +100 c tj 125 c 1 12.0 110 90 12.00 12.50 19.20 17.50 11.0 11.5 10 1 v dh = 15v t c = C20 c ~ +100 c (fig. 4) 0.8 2.5 2 integrated between input terminal-v dh t c 100 c, tj 125 c v dh = 15v, t c = C20 c ~ +100 c (note 3) relates to corresponding input (except brake part) t c = C20 c ~ +100 c relates to corresponding input (except brake part) condition symbol ratings v th(on) v th(off) r i f pwm t xx max. unit electrical characteristics (tj = 25 c, v dh = 15v, v db = 15v unless otherwise noted) (note 3) : (a) allowable minimum input on-pulse width : this item applies to p-side circuit only. (b) allowable maximum input on-pulse width : this item applies to both p-side and n-side circuits excluding the brake circuit. (note4) : cl output : the "current limit warning (cl) operation circuit outputs warning signal whenever the arm current exceeds this limit. the circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (note5) : the short circuit protection works instantaneously when a high short circuit current flows through an internal igbt ri sing up momen- tarily. the protection function is, thus meant primarily to protect the asipm against short circuit distraction. therefore, thi s function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due t o excessive temperature rise. instead, the analogue current output feature or the over load warning feature (cl) should be approp ri- ately used for such current regulation or over load control operation. in other words, the pwm signals to the asipm should be s hut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its f o1 pin of the asipm indicating a short circuit situation. allowable input on-pulse width allowable input signal dead time for blocking arm shoot-through input inter-lock sensing analogue signal linearity with output current offset change area vs temperature v dh = 15v, t c = C20 c ~ +100 c ic > i op (200%), v dh = 15v (fig. 4) analogue signal output voltage limit |v co -v c (200%)| analogue signal over all linear variation analogue signal data hold accuracy after input signal trigger point (fig. 8) analogue signal reading time current limit warning (cl) operation level v dh =15v open collector output 1 2.2 C5 4.77 open collector output 1.4 3.0 150 65 2.27 1.17 3.37 15 1.1 3 5.80 1 19.2 120 12.75 13.25 20.15 18.65 12.0 12.5 1 2.0 4.0 20 500 100 2.57 1.47 3.67 0.7 5 6.90 m a ma a c c v v v v v v m s m a ma v v k w khz m s m s ns v v v mv v v v % m s a pwm input frequency v dh =15v, t c = C20 c ~ +100 c (note 4) item t dead correspond to max. 500 m s data hold period only, ic = i op (200%) (fig. 5) r ch short circuit over current trip level signal output current of cl operation idle active tj = 25 c (fig. 7) (note 5) supply circuit under & over voltage protection over temperature protection fault output current i dh circuit current v dh = 15v, v cin = 5v ma v dh , v db control supply voltage applied between v dh -gnd, c bu+ -c buC , c bv+ -c bvC , c bw+ -c bwC using application circuit using application circuit 15 1.5 1 (max.) 0 ~ 0.3 4.8 ~ 5.0 2 ~ 20 2.2 (min.) v v/ m s v v khz m s
mitsubishi semiconductor PS11012 flat-base type insulated type jan. 2000 200 ?00 analogue output signal data hold range 1 2 3 4 5 400 300 100 0 ?00 ?00 ?00 0 v c +(200%) v c0 v c (200%) v c (v) v c + v c min max real load current peak value.(%)(i c =i o 5 2) v dh =15v t c = 20 ~ 100?c (fig. 4) fig. 4 output current analogue signaling linearity fig. 5 output current analogue signaling ?ata hold definition fig. 6 input interlock operation timing chart note : input interlock protection circuit ; it is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta- neously in ?ow level. by this interlocking, both upper and lower igbts of this mal-triggered phase are cut off, and ? o signal is outputted. after an ?nput interlock?operation the circuit is latched. the ? o is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. v ch (5 m s) v ch (505 m s) 0v v c 500 m s r ch = v ch (505 m s)-v ch (5 m s) v ch (5 m s) note ; ringing happens around the point where the signal output voltage changes state from ?nalogue?to ?ata hold?due to test circuit arrangement and instrumentational trouble. therefore, the rate of change is measured at a 5 m s delayed point. 0v 0v 0v 0v 0v input signal v cin(p) of each phase upper arm input signal v cin(n) of each phase lower arm gate signal v o(p) of each phase upper arm (asipm internal) gate signal v o(n) of each phase upper arm (asipm internal) error output f o1 fig. 7 timing chart and short circuit protection operation s c delay time short circuit sensing signal v s error output f o1 gate signal vo of each phase upper arm(asipm internal) input signal v cin of each phase upper arm 0v 0v 0v 0v note : short circuit protection operation. the protection operates with ? o flag and reset on a pulse-by-pulse scheme. the protection by gate shutdown is given only to the igbt that senses an overload (excluding the igbt for the ?rake?.
mitsubishi semiconductor PS11012 flat-base type insulated type jan. 2000 r u p ,v p ,w p ,u n ,v n ,w n ,br f 01 ,f 02 ,f 03 ,cl cu,cv,cw gnd(logic) asipm 5v cpu r 5.1k w 10k w 0.1nf 0.1nf on on on on 0 0 0 v pn dc-bus voltage control voltage supply boot-strap voltage n-side input signal p-side input signal brake input signal f o 1 output signal v db v cin(n) v cin(p) v cin(br) f oi v dh b) a) pwm starts fig. 8 inverter output analogue current sensing and signaling chart fig. 10 recommended i/o interface circuit n-side igbt current n-side fwdi current t(hold) td(read) delay time +i cl ? cl on off on off 0 0 on off 0 ref v cin v(hold) i c (v s ) v c v cl fig. 9 start-up sequence normally at start-up, fo and cl output signals will be pulled-up high to supply voltage (off level); however, f o1 output may fall to low (on) level at the instant of the first on input pulse to an n-side igbt. this can happen particularly when the boot-strap capacitor is of large size. f o1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph a) boot-strap charging scheme : apply a train of short on pulses at all n-igbt input pins for ad- equate charging (pulse width = approx. 20 m s number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) f o1 resetting sequence: apply on signals to the following input pins : br ? un/vn/wn ? up/vp/wp in that order.
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